T80C251TB 查看數據表（PDF） - Intel
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T80C251TB Datasheet PDF : 36 Pages
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8xC251TB/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.0 ADDRESS MAP
Table 8. 8xC251TB/TQ Address Map
Internal
Address)
Description
Notes
FF:FFFFH
FF:4000H
External Memory except the top eight bytes (FF:FFF8H–FF:FFFFH) which are
reserved for the configuration array.
1, 3, 10
FF:3FFFH
FF:0000H
External memory or on-chip nonvolatile memory (8Kbytes FF:0000H - FF:1FFFH, 3, 4, 5
16Kbytes FF:0000H - FF:3FFFH).
FE:FFFFH
FE:0000H
External Memory
3
FD:FFFFH Reserved
6
02:0000H
01:FFFFH
01:0000H
External Memory
3
00:FFFFH External memory or with configuration bit EMAP# = 0, addresses in this range
5, 7
00:E000H access on-chip code memory in region FF: (16 Kbyte devices only).
00:DFFFH
00:0420H
External Memory
7
00:041FH
00:0080H
On-chip RAM (512 bytes 00:0020H - 00:021FH, 1024 bytes 00:0020H - 00:041FH) 7
00:007FH
00:0020H
On-chip RAM
8
00:001FH
00:0000H
Storage for R0–R7 of Register File
2, 9
NOTES:
1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2. The special function registers (SFRs) and the register file have separate internal address spaces.
3. Data in this area is accessible by indirect addressing only.
4. Devices reset into internal or external starting locations depending on the state of EA# and configuration byte information
See EA#.
5. The 16-Kbyte ROM devices allow internal locations FF:2000H–FF:3FFFH to map into region 00:. In this case, if EA# = 1,
a data read to 00:E000H–00:FFFFH is redirected to internal ROM (see bit 1 in UCONFIG0). This is not available for 8-
Kbyte ROM devices.
6. This reserved area returns indeterminate values.
7. Data is accessible by direct and indirect addressing.
8. Data is accessible by direct, indirect, and bit addressing.
9. Data is accessible by direct, indirect, and register addressing.
10. Eight addresses at the top of all external memory maps are reserved for current and future device configuration byte
information.
11
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