IDT7007L15JI(1999) 查看數據表（PDF） - Integrated Device Technology
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IDT7007L15JI Datasheet PDF : 21 Pages
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IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Pin Configurations(1,2,3) (con't.)
Military, Industrial and Commercial Temperature Ranges
51 50 48 46 44 42 40 38 36
11
A5L A4L A2L A0L BUSYL M/S INTR A1R A3R
53 52 49 47 45 43 41 39 37 35 34
10 A7L A6L A3L A1L INTL GND BUSYR A0R A2R A4R A5R
55 54
09 A9L A8L
32 33
A7R A6R
57 56
08 A11L A10L
30 31
A9R A8R
59 58
07 VCC A12L
61 60
06 A14L A13L
63 62
05 SEML CEL
IDT7007G
G68-1(4)
68-Pin PGA
Top View(5)
28 29
A11R A10R
26 27
GND A12R
24 25
A14R A13R
65 64
04 OEL R/WL
22 23
SEMR CER
67 66
03 I/O0L N/C
20 21
OER R/WR
68 1
3
5
7
9
11 13 15 18 19
02 I/O1L I/O2L I/O4L GND I/O7L GND I/O1R VCC I/O4R I/O7R N/C
2
4
6
8
10 12 14 16 17
01
I/O3L I/O5L I/O6L VCC I/O0R I/O2R I/O3R I/O5R I/O6R
A
B
C
D
E
INDEX
NOTES:
1. All Vcc pins must be connected to power supply
2. All GND pins must be connected to power supply
3. Package body is approximately 1.8 in x 1.8 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
F
G
H
J
K
L
2940 drw 04
Pin Names
Left Port
Right Port
CEL
R/WL
CER
R/WR
OEL
OER
A0L - A14L
A0R - A14R
I/O0L - I/O7L
I/O0R - I/O7R
SEML
SEMR
INTL
INTR
BUSYL
BUSYR
M/S
VCC
GND
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2940 tbl 01
4
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