IDT7007L35PFB 查看數據表（PDF） - Integrated Device Technology
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IDT7007L35PFB Datasheet PDF : 22 Pages
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HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
IDT7007S/L
Features
◆ True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
◆ High-speed access
– Military: 25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
◆ Low-power operation
– IDT7007S
Active: 850mW (typ.)
Standby: 5mW (typ.)
– IDT7007L
Active: 850mW (typ.)
Standby: 1mW (typ.)
◆ IDT7007 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
◆ M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
◆ Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ TTL-compatible, single 5V (±10%) power supply
◆ Available in 68-pin PGA and PLCC and a 80-pin TQFP
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Green parts available, see ordering information
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A14L
A0L
I/O
Control
I/O
Control
Address
Decoder
15
CEL
OEL
R/WL
MEMORY
ARRAY
15
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL(2)
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
1
©2014 Integrated Device Technology, Inc.
Address
Decoder
CER
OER
R/WR
I/O0R-I/O7R
BUSYR(1,2)
A14R
A0R
SEMR
INTR(2)
2940 drw 01
AUGUST 2014
DSC 2940/14
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