IDT707288L15PFI 查看數據表（PDF） - Integrated Device Technology
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IDT707288L15PFI
Integrated Device Technology
IDT707288L15PFI Datasheet PDF : 16 Pages
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IDT707288S/L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
OE
tHZ (7)
tAW
CE or (9,10)
MBSEL
UB or LB (9)
R/W
DATAOUT
DATAIN
tAS (6)
tLZ
tWP(2)
tWZ (7)
VALID(4)
tDW
tWR(3)
tOW
tDH
(4)
3592 drw 08
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
CE or MBSEL(9,10)
UB or LB (9)
(6)
tAS
tAW
tEW (2)
tWR(3)
R/W
DATAIN
tDW
tDH
3592 drw 09
NOTES:
1. R/W or CE or UB and LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or MBSEL or R/W) going to VIH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or MBSEL = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
tWP.
9. To access RAM, CE = VIL and MBSEL = VIH. To access mailboxes, CE = VIH and MBSEL = VIL. tEW must be met for either condition.
10. Refer to Truth Table I.
61.422
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