IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUSY (M/S = VIH)(2,4,5)
ADDR"A"
W R/ "A"
DATAIN "A"
tAPS (1)
ADDR"B"
BUSY"B"
DATAOUT "B"
tWC
MATCH
tWP
tDW
tDH
VALID
tBAA
MATCH
tBDA
tWDD
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite Port from Port "A".
tBDD
VALID
2683 drw 13
TIMING WAVEFORM OF WRITE WITH BUSY
W R/ "A"
BUSY"B"
tWP
tWB( 3 )
W R/ "B"
(2)
NOTES:
1. tWH must be met for both BUSY input (slave) output master.
2. Busy is asserted on port "B" Blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the 'Slave' Version.
tWH ( 1 )
2683 drw 14
6.16
13