IDT7025S17F(1996) 查看數據表（PDF） - Integrated Device Technology

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IDT7025S17F
(Rev.:1996)

HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7025S/L

HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE IV —

ADDRESS BUSY ARBITRATION

Inputs

Outputs

A0L-A12L

CEL CER A0R-A12R BUSYL(1) BUSYR(1)

Function

X

X NO MATCH

H

H

Normal

H

X

MATCH

H

H

Normal

X

H

MATCH

H

L

L

MATCH

(2)

H

Normal

(2)

Write Inhibit(3)

NOTES:

2683 tbl 18

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the

IDT7025 are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable

after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low

simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are

internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.

TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)

Functions

D0 - D15 Left D0 - D15 Right

Status

No Action

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

Right Port Writes "0" to Semaphore

0

1

No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore

1

0

Right port obtains semaphore token

Left Port Writes "0" to Semaphore

1

0

No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore

0

1

Left port obtains semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

Right Port Writes "0" to Semaphore

1

0

Right port has semaphore token

Right Port Writes "1" to Semaphore

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7025.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.

2683 tbl 19

FUNCTIONAL DESCRIPTION

The IDT7025 provides two ports with separate control, writes to memory location 1FFF (HEX) and to clear the

address and I/O pins that permit independent access for reads interrupt flag (INTR), the right port must access the memory

or writes to any location in memory. The IDT7025 has an location 1FFF, The message (16 bits) at 1FFE or 1FFF is user-

automatic power down feature controlled by CE. The CE defined, since it is an addressable SRAM location. If the

controls on-chip power down circuitry that permits the interrupt function is not used, address locations 1FFE and

respective port to go into a standby mode when not selected 1FFF are not used as mail boxes, but as part of the random

(CE High). When a port is enabled, access to the entire access memory. Refer to Truth Table for the interrupt opera-

memory array is permitted.

tion.

INTERRUPTS

If the user chooses to use the interrupt function, a memory

location (mail box or message center) is assigned to each port.

The left port interrupt flag (INTL) is asserted when the right port

writes to memory location 1FFE (HEX), where a write is

defined as the CER = R/WR = VIL per the Truth Table. The left

port clears the interrupt by an address location 1FFE access

when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the

right port interrupt flag (INTR) is asserted when the left port

BUSY LOGIC

Busy Logic provides a hardware indication that both ports

of the RAM have accessed the same location at the same

time. It also allows one of the two accesses to proceed and

signals the other side that the RAM is “Busy”. The busy pin can

then be used to stall the access until the operation on the other

side is completed. If a write operation has been attempted

from the side that receives a busy indication, the write signal

is gated internally to prevent the write from proceeding.

6.16

16

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