IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Port-to-Port Read and BUSY(2,4,5) (M/S = VIH)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN "A"
tAPS (1)
VALID
ADDR"B"
BUSY"B"
tBAA
MATCH
tBDA
tBDD
tWDD
DATAOUT "B"
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input. Therefore in this example BUSY"A" = VIH and BUSY"B" input is shown.
5. All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite port from Port "A".
VALID
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Timing Waveform of Write with BUSY
R/W"A"
tWP
BUSY"B"
tWB(3)
R/W"B"
(2)
NOTES:
1. tWH must be met for both BUSY input (slave) output master.
2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'Slave' Version.
tWH(1)
2683 drw 14 .
6.1442