IDT7015S17JG 查看數據表（PDF） - Integrated Device Technology
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IDT7015S17JG Datasheet PDF : 20 Pages
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IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7015X12
Com'l Only
7015X15
Com'l Only
7015X17
Com'l Only
Symbol
BUSY TIMING (M/S = VIH)
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
tBAA
BUSY Access Time from Address
____
12
____
15
____
17
ns
tBDA
BUSY Disable Time from Address
____
12
____
15
____
17
ns
tBAC
BUSY Access Time from Chip Enable
____
12
____
15
____
17
ns
tBDC
BUSY Disable Time from Chip Enable
tAPS
Arbitration Priority Set-up Time(2)
____
12
____
15
____
17
ns
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
tWH
Write Hold After BUSY(5)
BUSY INPUT TIMING (M/S = VIL)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
____
15
____
18
____
18
ns
11
____
13
____
13
____
ns
0
____
0
____
0
____
ns
11
____
13
____
13
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
25
____
30
____
40
ns
____
20
____
25
____
35
ns
7015X20
Com'l, Ind
& Military
7015X25
Com'l &
Military
7015X35
Com'l &
Military
2954 tbl 14a
Symbol
BUSY TIMING (M/S = VIH)
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
tBAA
BUSY Access Time from Address
____
20
____
20
____
20
ns
tBDA
BUSY Disable Time from Address
____
20
____
20
____
20
ns
tBAC
BUSY Access Time from Chip Enable
____
20
____
20
____
20
ns
tBDC
BUSY Disable Time from Chip Enable
tAPS
Arbitration Priority Set-up Time(2)
____
17
____
17
____
20
ns
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
tWH
Write Hold After BUSY(5)
BUSY INPUT TIMING (M/S = VIL)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
____
30
____
30
____
35
ns
15
____
17
____
25
____
ns
0
____
15
____
0
____
17
____
0
____
ns
25
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
45
____
50
____
60
ns
____
30
____
35
____
45
ns
NOTES:
2954 tbl 14b
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
61.422
APRIL 04, 2006
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