IDT7015S17GI 查看數據表（PDF） - Integrated Device Technology
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IDT7015S17GI Datasheet PDF : 20 Pages
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IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Waveform of Interrupt Timing(1)
tWC
Military, Industrial and Commercial Temperature Ranges
ADDR"A"
CE"A"
tAS(3)
INTERRUPT SET ADDRESS (2)
tWR (4)
R/W"A"
INT"B"
ADDR"B"
CE"B"
tINS (3)
tAS(3)
tRC
INTERRUPT CLEAR ADDRESS (2)
2954 drw 17
OE"B"
INT"B"
tINR (3)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
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Truth Table III — Interrupt Flag(1)
Left Port
R/WL
CEL
OEL
A12L-A0L
INTL
R/WR
L
L
X
1FFF
X
X
X
X
X
X
X
X
X
X
X
X
L(3)
L
X
L
L
1FFE
H(2)
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Right Port
CER
OER
A12R-A0R
X
X
X
L
L
1FFF
L
X
1FFE
X
X
X
INTR
Function
L(2) Set Right INTR Flag
H(3) Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
2954 tbl 16
61.452
APRIL 04, 2006
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