ISL62882B 查看數據表（PDF） - Intersil

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产品描述 (功能)

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ISL62882B

Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

Intersil 

ISL62882, ISL62882B

Functional Pin Descriptions (Continued)

ISL62882 ISL62882B

24

29

-

-

25

30

26

32

27

33

28

34

29

35

30

36

31 thru 37 38 thru 44

38

45

39

46

40

47

-

48

pad

pad

SYMBOL

LGATE1b

LGATE1

VCCP

LGATE2

VSSP2

PHASE2

UGATE2

BOOT2

VID0 thru VID6

VR_ON

DPRSLPVR

CLK_EN#

NC

BOTTOM

DESCRIPTION

Another output of the Phase-1 low-side MOSFET gate driver. This gate driver will

be pulled low when the DPRSLPVR pin logic is high. Connect the LGATE1b pin to

the gate of the Phase-1 low-side MOSFET that is idle in deeper sleep mode.

Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to

the gate of the Phase-1 low-side MOSFET.

Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin.

Decouple with at least 1µF of an MLCC capacitor to VSSP1 and VSSP2 pins

respectively.

Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to

the gate of the Phase-2 low-side MOSFET.

Current return path for the Phase-2 converter low-side MOSFET gate driver.

Connect the VSSP2 pin to the source of the Phase-2 low-side MOSFET through a

low impedance path, preferably in parallel with the trace connecting the LGATE2

pin to the gate of the Phase-2 low-side MOSFET.

Current return path for the Phase-2 high-side MOSFET gate driver. Connect the

PHASE2 pin to the node consisting of the high-side MOSFET source, the low-side

MOSFET drain, and the output inductor of Phase-2.

Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to

the gate of the Phase-2 high-side MOSFET.

Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot

capacitor is charged through an internal boot diode connected from the VCCP pin

to the BOOT2 pin, each time the PHASE2 pin drops below VCCP minus the voltage

dropped across the internal boot diode.

VID input with VID0 = LSB and VID6 = MSB.

Voltage regulator enable input. A high level logic signal on this pin enables the

regulator.

Deeper sleep enable signal. A high level logic signal on this pin indicates that the

microprocessor is in deeper sleep mode.

Open drain output to enable system PLL clock. It goes low 13 switching cycles

after Vcore is within 10% of Vboot.

No connect.

The bottom pad of ISL62882B is electrically connected to the GND pin inside the

IC.

4

FN6890.2

April 29, 2010

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