MAX9673ETI 查看數據表（PDF） - Maxim Integrated

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MAX9673ETI

10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs

Maxim Integrated 

10-Bit, Programmable Gamma Reference

Systems with MTP for TFT LCDs

proper slave address followed by the register address

and then the data word. Each transmit sequence is

framed by a START (S) or REPEATED START (Sr) condi-

tion and a STOP (P) condition. Each byte is serially trans-

mitted to the MAX9672/MAX9673/MAX9674 as 8 bits and

is followed by an acknowledge clock pulse. A master

reading data from the MAX9672/MAX9673/MAX9674

transmit the proper slave address followed by a series of

nine SCL pulses. The MAX9672/MAX9673/MAX9674

transmit data on SDA in sync with the master-generated

SCL pulses. The master acknowledges receipt of each

byte of data. Each read sequence is framed by a START

or REPEATED START condition, a not acknowledge, and

a STOP condition. SDA operates as both an input and an

open-drain output. A pullup resistor, typically greater

than 500Ω, is required on the SDA bus. SCL operates as

only an input. A pullup resistor, typically greater than

500Ω, is required on SCL if there are multiple masters on

the bus, or if the master in a single-master system has an

open-drain SCL output. Series resistors in line with SDA

and SCL are optional. Series resistors protect the digital

inputs of the MAX9672/MAX9673/MAX9674 from high-

voltage spikes on the bus lines, and minimize crosstalk

and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL cycle. The

data on SDA must remain stable during the high period

of the SCL pulse. Changes in SDA while SCL is high

are control signals (see the START and STOP

Conditions section). SDA and SCL idle high when the

I2C bus is not busy.

START and STOP Conditions

SDA and SCL idle high when the bus is not in use. A

master initiates communication by issuing a START con-

dition. A START condition is a high-to-low transition on

SDA with SCL high. A STOP condition is a low-to-high

transition on SDA while SCL is high (Figure 2). A START

condition from the master signals the beginning of a

transmission to the MAX9672/MAX9673/MAX9674. The

master terminates transmission, and frees the bus, by

issuing a STOP condition. The bus remains active if a

REPEATED START condition is generated instead of a

STOP condition.

Early STOP Conditions

The MAX9672/MAX9673/MAX9674 use a STOP condi-

tion at any point during data transmission except if the

STOP condition occurs in the same high pulse as a

START condition. For proper operation, do not send a

STOP condition during the same SCL high pulse as the

START condition.

Table 1. Slave Address

A0

GND

DVDD

READ ADDRESS

E9h

EBh

S

Sr

SCL

WRITE ADDRESS

E8h

EAh

P

SDA

Figure 2. START, STOP, and REPEATED START Conditions

START

CONDITION

SCL

1

2

CLOCK PULSE FOR

ACKNOWLEDGMENT

8

9

SDA

Figure 3. Acknowledge

NOT ACKNOWLEDGE

ACKNOWLEDGE

Slave Address

The slave address is defined as the 7 most significant

bits (MSBs) followed by the read/write (R/W) bit. Set the

R/W bit to 1 to configure the MAX9672/MAX9673/

MAX9674 to read mode. Set the R/W bit to 0 to config-

ure the MAX9672/MAX9673/MAX9674 to write mode.

The address is the first byte of information sent to the

MAX9672/MAX9673/MAX9674 after the START condi-

tion. The MAX9672/MAX9673/MAX9674 slave address

is configured with A0. Table 1 shows the possible

addresses for the MAX9672/MAX9673/MAX9674.

Acknowledge

The acknowledge bit (ACK) is a clocked 9th bit that the

MAX9672/MAX9673/MAX9674 use to handshake

receipt of each byte of data when in write mode (see

Figure 3). The MAX9672/MAX9673/MAX9674 pull down

SDA during the entire master-generated ninth clock

pulse if the previous byte is successfully received.

Monitoring ACK allows for detection of unsuccessful

data transfers. An unsuccessful data transfer occurs if

10 ______________________________________________________________________________________

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