PLCDA03C-6(2005) 查看數據表（PDF） - ProTek Devices.
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PLCDA03C-6 Datasheet PDF : 5 Pages
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APPLICATION NOTE
PLCDA03C-6
thru
PLCDA15C-6
The PLCDAxxC-6 Series are low capacitance, bidirectional TVS arrays that are designed to protect I/O or high speed data lines from the damaging
effects of ESD or EFT. This product series has a surge capability of 500 Watts PPP per line for an 8/20µs waveshape and offers ESD protection >
40kv.
BIDIRECTIONAL COMMON-MODE CONFIGURATION (Figure 1)
Ideal for use multimode transceiver I/O lines, the PLCDAxxC-6 Series provides up
to six (6) lines of protection in a common-mode configuration as depicted in Figure
1.
Circuit connectivity is as follows:
✔ Line 1 is connected to Pin 1.
✔ Line 2 is connected to Pin 2.
✔ Line 3 is connected to Pin 3.
✔ Line 4 is connected to Pin 8.
✔ Line 5 is connected to Pin 7.
✔ Line 6 is connected to Pin 6.
✔ Pins 4 and 5 are connected to Ground.
Figure 1: Typical Transceiver Protection Circuit
LINE 6
LINE 5
LINE 4
LINE 3
LINE 2
LINE 1
1
8
BIDIRECTIONAL COMMON-MODE CONFIGURATION (Figure 2)
The PLCDAxxC-6 Series also provides video line applications six (6) lines of
protection in a common-mode configuration as depicted in Figure 2.
Circuit connectivity is as follows:
✔ Line 1 (Red) is connected to Pin 1.
✔ Line 2 (Green) is connected to Pin 2.
✔ Line 3 (Blue) is connected to Pin 3.
✔ Line 4 (VSYNC) is connected to Pin 6.
✔ Line 5 (HSYNC) is connected to Pin 7.
✔ Pins 4 and 5 are connected to Ground.
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Circuit board layout is critical for Electromagnetic
Compatibility (EMC) protection. The following
guidelines are recommended:
✔ The protection device should be placed near the
input terminals or connectors, the device will
divert the transient current immediately before it
can be coupled into the nearby traces.
✔ The path length between the TVS device and
the protected line should be minimized.
✔ All conductive loops including power and ground
loops should be minimized.
✔ The transient current return path to ground
should be kept as short as possible to reduce
parasitic inductance.
✔ Ground planes should be used whenever
possible. For multilayer PCBs, use ground vias.
2
7
3
6
4
5
Figure 2: Typical Video Line Protection Circuit
LINE 1 (RED)
LINE 2 (GREEN)
LINE 3 (BLUE)
4
3
2
1
5
6
7
8
LINE 4 (VSYNC)
LINE 4 (HSYNC)
DB-15
CONNECTOR
05102.R6 4/05
4
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