83C196MC 查看數據表（PDF） - Intel
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83C196MC Datasheet PDF : 22 Pages
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8XC196MC
87C196MC DESIGN
CONSIDERATIONS
When an indirect shift during divide occurs the upper
3 bits of the shift count are not masked completely
If the shift count register has the value 32 n where n
e 1 3 5 or 7 the operand will be shifted 32 times
This should have resulted in no shift taking place
DATA SHEET REVISION HISTORY
This data sheet (270946-004) is valid for devices
with a ‘‘B’’ at the end of the topside tracking number
Data sheets are changed as new device information
becomes available Verify with your local Intel sales
office that you have the latest version before finaliz-
ing a design or ordering devices
The following important differences exist between
this data sheet (270946-002) and the previous ver-
sion (270946-003)
1 The data sheet was reorganized to standard for-
mat
2 Added 83C196MC device
3 Added package thermal characteristics
4 Added note on missing pins on SDIP package
5 Removed SFR maps (now in user’s manual)
6 Added note on TLLYV and TLLGV specifications
7 Changed 10-bit mode TCONV (MIN) to 10 0 ms
from 15 0 ms
8 Changed 10-bit mode TCONV (MAX) to 20 0 ms
from 18 0 ms
9 Changed VREF (MIN) in 8- and 10-bit mode to
4 0V from 4 5V
The following important differences exist between
data sheet 270946-003 and the previous version
(270946-002)
1 The data sheet title was changed to better reflect
the purpose of the 87C196MC as an AC Inverter
DC Brushless Motor Control Microcontroller
2 The standard temperature range for this part now
covers b40 C to a85 C
3 EXTINT function description now includes
WG PROTECT (1FCEH) as the name and ad-
dress of the register used to select positive neg-
ative or high low detection for EXTINT
4 The memory range 01F00H – 01FBFH was added
to the SFR map as RESERVED
5 IIL changed from b60 mA to b70 mA
6 IREF changed from 5 mA to 2 mA maximum and
the typical specification was removed
7 The READY description of the READY TIMINGS
(One Wait State) graphic was modified to denote
the shifting of the leading edge of READY versus
frequency At 16 MHz the falling edge of READY
occurs before the falling edge of ALE
8 AC Testing Input Output Waveform was
changed to reflect inputs driven at 3 5V for a
Logic ‘‘1’’ and 45V for a Logic ‘‘0’’ and timing
measurements made at 2 0V for a Logic ‘‘1’’
and 0 8V for a Logic ‘‘0’’
9 Float Waveform was changed from IOL IOH e
g15 mA to IOL IOH s g15 mA
10 AD TIME register for 10-bit conversions was
changed from 0C7H to 0D8H The number of
sample time states was changed from 24 to 25
states the conversion time states was changed
from 80 to 240 states and the total conversion
time for AD TIME e D8H replaced the total
conversion time for AD TIME e C7H
11 The number of sample time states for an 8-bit
conversion was changed from 20 states to 21
states
12 There is a single entry in the ERRATA section of
this version of the data sheet concerning the
results of an indirect shift during divide
The following important differences exist between
this data sheet (270946-002) and the previous ver-
sion (270946-001)
1 TA Ambient Temperature Under Bias Min
changed from b20 C to b40 C
2 IREF A D Conversion Reference Current Max
changed from 5 mA to 2 mA
3 Testing levels changed from TTL values to
CMOS values
4 A D Input Series Resistance Max changed from
1 2 KX to 2 KX
22
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