ALC5633 查看數據表（PDF） - Realtek Semiconductor
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ALC5633 Datasheet PDF : 87 Pages
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MCLK
N
19.68
78
ALC5633Q
Datasheet
M
FVCO
K
FOUT
14
98.4
2
24.6
MCLK
13
3.6864
2.048
4.096
12
15.36
16
19.2
19.68
Table 8.
N
68
72
86
64
66
63
66
64
67
Clock Setting Table for 44.1K (Unit: MHz)
M
FVCO
K
8
91
2
1
90.931
2
0
90.112
2
1
90.112
2
7
90.667
2
9
90.764
2
10
90.667
2
12
90.514
2
13
90.528
2
FOUT
22.75
22.733
22.528
22.528
22.667
22.691
22.667
22.629
22.632
After a POR Reset, PLL related Registers are reset to default values, however, they are not reset to
default values after a soft-reset (write REG-MX00). Firmware should not power down the PLL when the
PLL output is used as system clock.
7.3.2. I2C and Stereo I2S
The ALC5633Q supports I2C for the digital control interface, and has I2S/PCM for the digital data
interface. The I2S/PCM audio digital interface is used to input data to a stereo DAC or output data from a
stereo ADC. The I2S/PCM audio digital interface can be configured to Master mode or Slave mode.
Master Mode
In master mode BCLK and LRCK are configured as output.
When MCLK is used as I2S SYSCLK source, PLL can be disabled and sel_sysclk=0’b. The MCLK is
used as system clock.
When PLL output is used as I2S SYSCLK source PLL enabled and sel_sysclk=1’b, PLL should be
configured to support 256 or 384*Fs onto I2S SYSCLK.
Slave Mode
In slave mode BCLK and LRCK are configured as input. The I2S SYSCLK can be input from MCLK by
providing BCLK synchronized clock externally or from BCLK with PLL to generate 256 or 384*Fs as
I2S SYSCLK. The driver should set each divider to arrange the clock distribution.
I2S Stereo Audio Codec + Mono Class-AB/D Amp
9
Rev. 0.1
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