LF3320 查看數據表（PDF） - LOGIC Devices Incorporated

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LF3320

Horizontal Digital Image Filter

LOGIC Devices Incorporated 

DEVICES INCORPORATED

LF3320

Horizontal Digital Image Filter

Registers on the rising edge of CLK.

When SHENB is HIGH, data can not be

loaded into the Cascade Registers or

shifted through the I/D Registers and

their contents will not be changed.

In Single Filter Mode, SHENB also

enables or disables the loading of data

into the Input (DIN11-0), Reverse

Cascade Output (ROUT11-0) and Filter

A I/D Registers. It is important to note

that in Single Filter Mode, both

SHENA and SHENB should be

connected together. Both must be

active to enable data loading in Single

Filter Mode. SHENB is latched on the

rising edge of CLK.

ROUT3-0 are enabled for output. When

OEC is HIGH, COUT11-0 and ROUT3-0

are placed in a high-impedance state.

PAUSEA — LF InterfaceTM Pause

When PAUSEA is HIGH, the Filter A

LF InterfaceTM loading sequence is

halted until PAUSEA is returned to a

LOW state. This effectively allows the

user to load coefficients and control

registers at a slower rate than the

master clock (see the LF InterfaceTM

section for a full discussion).

FIGURE 4. SINGLE FILTER MODE

PAUSEB — LF InterfaceTM Pause

When PAUSEB is HIGH, the Filter B LF

InterfaceTM loading sequence is halted

until PAUSEB is returned to a LOW

state. This effectively allows the user

to load coefficients and control regis-

ters at a slower rate than the master

clock (see the LF InterfaceTM section for

a full discussion).

RSLA3-0 — Filter A Round/Select/Limit

Control

RSLA3-0 determines which of the

sixteen user-programmable Round/

Select/Limit registers (RSL registers)

are used in the Filter A RSL circuitry.

A value of 0 on RSLA3-0 selects RSL

register 0. A value of 1 selects RSL

register 1 and so on. RSLA3-0 is

latched on the rising edge of CLK (see

the round, select, and limit sections for

a complete discussion).

RSLB3-0 — Filter B Round/Select/Limit

Control

12

ROUT11-0

12

DIN11-0

I/D

REGISTERS

FILTER

A

RSL

CIRCUIT

16

DOUT15-0

I/D

REGISTERS

12

RIN11-0

12

COUT11-0

FILTER

B

RSLB3-0 determines which of the sixteen

user-programmable RSL registers are

used in the Filter B RSL circuitry. A

value of 0 on RSLB3-0 selects RSL

register 0. A value of 1 selects RSL

register 1 and so on. RSLB3-0 is latched

on the rising edge of CLK (see the round,

select, and limit sections for a complete

discussion).

FIGURE 5. DUAL FILTER MODE

12

DIN11-0

I/D

REGISTERS

FILTER

A

I/D

REGISTERS

FILTER

B

12

RIN11-0

OED — DOUT Output Enable

When OED is LOW, DOUT15-0 is

enabled for output. When OED is

HIGH, DOUT15-0 is placed in a high-

impedance state.

OEC — COUT/ROUT Output Enable

When OEC is LOW, COUT11-0 and

R.S.L.

CIRCUIT

16

DOUT15-0

R.S.L.

CIRCUIT

16

ROUT3-0 / COUT11-0

Video Imaging Products

2-5

08/16/2000–LDS.3320-N

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