LTC1164-6(Rev0) 查看數據表（PDF） - Linear Technology
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LTC1164-6
(Rev.:Rev0)
(Rev.:Rev0)
Linear Technology
LTC1164-6 Datasheet PDF : 12 Pages
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LTC1164-6
PI FU CTIO S (14-Lead Dual-In-Line Package)
level threshold value for a dual or single supply operation.
A pulse generator can be used as a clock source provided
the high level ON time is greater than 0.5µs. Sine waves are
not recommended for clock input frequencies less than
100kHz, since excessively slow clock rise or fall times
generate internal clock jitter (maximum clock rise or fall
time ≤ 1µs). The clock signal should be routed from the
right side of the IC package to avoid coupling into any input
or output analog signal path. A 1k resistor between clock
source and pin 11 will slow down the rise and fall times of
the clock to further reduce charge coupling, Figures 1
and 2.
1
VIN
2
3
V–
14
*
13 0.1µF
12
V+
4 LTC1164-6 11
1k
CLOCK SOURCE
5
10
6
9
0.1µF
7
8
GND
+
DIGITAL SUPPLY
* OPTIONAL
VOUT
1164-6 F01
Figure 1. Dual Supply Operation for fCLK/fCUTOFF = 100:1
VIN
V+
10k
10k
1
14
2
13
0.1µF
3
12
4 LTC1164-6 11
5
10
6
9
7
8
1k
CLOCK SOURCE
GND
+
DIGITAL SUPPLY
+
1µF
VOUT
1164-6 F02
Figure 2. Single Supply Operation for fCLK/fCUTOFF = 100:1
Table 1. Clock Source High and Low Threshold Levels
POWER SUPPLY
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ±2.5V
Single Supply = 12V
Single Supply = 5V
HIGH LEVEL
≥ 2.18V
≥ 1.45V
≥ 0.73V
≥ 7.80V
≥ 1.45V
LOW LEVEL
≤ 0.5V
≤ 0.5V
≤ – 2.0V
≤ 6.5V
≤ 0.5V
Analog Ground Pins (3, 5)
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the pack-
age is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, pins 3 and 5 should be connected to the
analog ground plane. For single supply operation pins 3
and 5 should be biased at 1/2 supply and they should be
bypassed to the analog ground plane with at least a 1µF
capacitor (Figure 2). For single 5V operation at the highest
fCLK of 1MHz, pins 3 and 5 should be biased at 2V. This
minimizes passband gain and phase variations (see Typi-
cal Performance Characteristics curves: Maximum Pass-
band for Single 5V, 50:1; and THD + Noise vs RMS Input
for Single 5V, 50:1).
Elliptic/Linear Phase Select Pin (10)
The DC level at this pin selects the desired filter response,
elliptic or linear phase and determines the ratio of the clock
frequency to the cutoff frequency of the filter. Pin 10
connected to V – provides an elliptic lowpass filter with
clock-to-fCUTOFF ratio of 100:1. Pin 10 connected to
analog ground provides a linear phase lowpass filter with
a clock- to-f–3dB ratio of
overshoot of 1%. When
160:1 and
pin 10 is
a transient
connected
response
to V+ the
clock-to-fCUTOFF ratio is 50:1 and the filter response is
elliptic. Bypassing pin 10 to analog ground reduces the
output DC offsets. If the DC level at pin 10 is switched
mechanically or electrically at slew rates greater than 1V/
µs while the device is operating, a 10k resistor should be
connected between pin 10 and the DC source.
Filter Input Pin (2)
The input pin is connected internally through a 50k resis-
tor tied to the inverting input of an op amp.
Filter Output Pins (9, 6)
Pin 9 is the specified output of the filter; it can typically
source or sink 1mA. Driving coaxial cables or resistive
loads less than 20k will degrade the total harmonic distor-
tion of the filter. When evaluating the device’s distortion an
output buffer is required. A noninverting buffer, Figure 3,
7
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