MPC5200VR400B(2006) 查看數據表（PDF） - Freescale Semiconductor

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MPC5200VR400B
(Rev.:2006)

SDRAM/DDR Memory Controller

Freescale Semiconductor 

Electrical and Thermal Characteristics

Table 15. Reset Rise / Fall Timing

Description

PORRESET fall time

PORRESET rise time

HRESET fall time

HRESET rise time

SRESET fall time

SRESET rise time

Min

Max

Unit

SpecID

—

1

ms

A3.4

—

1

ms

A3.5

—

1

ms

A3.6

—

1

ms

A3.7

—

1

ms

A3.8

—

1

ms

A3.9

NOTES:

Make sure that the PORRESET does not carry any glitches. The MPC5200B has no filter to prevent them from getting into the

chip.

HRESET and SRESET must have a monotonous rise time.

The assertion of HRESET becomes active at Power on Reset without any SYS_XTAL clock.

For additional information, see the MPC5200B User Manual [1].

3.3.3.1 Reset Configuration Word

During reset (HRESET and PORRESET) the Reset Configuration Word is latched in the related Reset

Configuration Word Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET and

PORRESET) are inactive (high), the contents of this register will be locked immediately with the

SYS_XTAL clock (see Figure 3).

SYS_XTAL

4096 clocks

PORRESET

HRESET

RST_CFG_WRD

sample sample sample sample

sample sample sample sample

sample

sample

LOCK

Figure 3. Reset Configuration Word Locking

MPC5200B Data Sheet, Rev. 1

Freescale Semiconductor

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