MPC5200B(2006) 查看數據表（PDF） - Freescale Semiconductor

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MPC5200B
(Rev.:2006)

SDRAM/DDR Memory Controller

Freescale Semiconductor 

Electrical and Thermal Characteristics

Table 19. Standard SDRAM Write Timing

Sym

tmem_clk

tvalid

thold

DMvalid

DMhold

datavalid

datahold

Description

Min

MEM_CLK period

7.5

Control Signals, Address and MBA Valid

—

after rising edge of MEM_CLK

Control Signals, Address and MBA Hold after

rising edge of MEM_CLK

tmem_clk*0.5

DQM valid after rising edge of MEM_CLK

—

DQM hold after rising edge of Mem_clk

MDQ valid after rising edge of MEM_CLK

tmem_clk*0.25-0.7

—

MDQ hold after rising edge of MEM_CLK

tmem_clk*0.75-0.7

Max

—

tmem_clk*0.5+0.4

—

tmem_clk*0.25+0.4

—

tmem_clk*0.75+0.4

—

Units SpecID

ns

A5.8

ns

A5.9

ns A5.10

ns A5.11

ns A5.12

ns A5.13

ns A5.14

MEM_CLK

Control Signals

DQM (Data Mask)

MDQ (Data)

MA (Address)

MBA (Bank Selects)

tvalid

thold

Active

NOP WRITE

NOP

DMvalid

DMhold

NOP NOP

datavalid

tvalid

tvalid

thold

Row

thold

datahold

Column

NOP

NOP

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing

3.3.5.3 Memory Interface Timing-DDR SDRAM Read Command

The SDRAM Memory Controller uses a 1/4 period delayed MDQS strobe to capture the MDQ data. The

1/4 period delay value is calculated automatically by hardware.

MPC5200B Data Sheet, Rev. 1

Freescale Semiconductor

21

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