MPC5200B 查看數據表（PDF） - Freescale Semiconductor

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MPC5200B

SDRAM/DDR Memory Controller

Freescale Semiconductor 

MEM_CLK

MEM_CLK

Control Signals

tvalid

thold

Active NOP

READ

NOP

NOP NOP NOP NOP

MDQS (Data Strobe)

MDQ (Data)

Read Data

Sample Window

tdata_valid_min

tdata_valid_max

tdata_sample_min

tdata_sample_max

Sample

position

A

MDQS (Data Strobe)

MDQ (Data)

Read Data

Sample Window

tdata_valid_min

tdata_valid_max

0.5 × tMEM_CLK

tdata_sample_min

tdata_sample_max

Sample

position

B

tvalid

MA (Address)

tvalid

MBA (Bank Selects)

thold

Row

thold

Column

Sample position A: data are sampled on the expected edge of MEM_CLK, the MDQS signal indicate the valid data

Sample position B: data are sampled on a later edge of MEM_CLK, SDRAM controller is waiting for the valid MDQS signal

NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing

MPC5200B Data Sheet, Rev. 4

20

Freescale Semiconductor

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