MPC5200B 查看數據表（PDF） - Freescale Semiconductor

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MPC5200B

SDRAM/DDR Memory Controller

Freescale Semiconductor 

1.3.6.4 Memory Interface Timing-DDR SDRAM Write Command

Table 21. DDR SDRAM Memory Write Timing

Sym

Description

Min

tmem_clk

MEM_CLK period

7.5

tDQSS Delay from write command to first

—

rising edge of MDQS

datavalid MDQ valid before rising edge of

1.0

MDQS

datahold

MDQ valid after rising edge of

1.0

MDQS

Max

—

tmem_clk + 0.4

—

—

Units SpecID

ns A5.20

ns A5.21

ns A5.22

ns A5.23

MEM_CLK

MEM_CLK

Control Signals Write

MDQS (Data Strobe)

tDQSS

Write

datavalid

datahold

MDQ (Data)

Write

Write

NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1, and CLK_EN

Figure 8. DDR SDRAM Memory Write Timing

1.3.7 PCI

The PCI interface on the MPC5200B is designed to PCI Version 2.2 and supports 33 MHz and 66 MHz PCI operations. See the

PCI Local Bus Specification; the component section specifies the electrical and timing parameters for PCI components with the

intent that components connect directly together whether on the planar or an expansion board, without any external buffers or

other “glue logic.” Parameters apply at the package pins, not at expansion board edge connectors.

The MPC5200B is always the source of the PCI CLK. The clock waveform must be delivered to each 33 MHz or 66 MHz PCI

component in the system. Figure 9 shows the clock waveform and required measurement points for 3.3 V signaling

environments. Table 22 summarizes the clock specifications.

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

21

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