STK672-630A-E 查看數據表（PDF） - ON Semiconductor
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STK672-630A-E Datasheet PDF : 21 Pages
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STK672-630A-E
Figure 2 Substrate temperature rise, ΔTc (no heat sink) - Internal average power dissipation, PdAV
ΔTc - PdAV
80
70
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Hybrid IC internal average power dissipation, PdAV - W
3.5
ITF02553
Figure 3 Heat sink area (Board thickness: 2mm) - θc-a
θc-a - S
100
7
5
3
2
10
7
5
3
2
With
With
a flat
nbolascukrfsaucrefafcienifsihnish
1.0
10
23
5 7 100
23
Heat sink area, S - cm2
5 7 1000
ITF02554
6. Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta
Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink.
The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta.
Power loss of up to 3.1W is allowable at Ta=25°C, and of up to 1.75W at Ta=60°C.
Allowable power dissipation, PdPK(no heat sink) - Ambient temperature, Ta
PdPK - Ta
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
80
100
120
Ambient temperature,Ta - °C
ITF02511
No. A1129-19/21
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