WM8778SEDS/RV 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8778SEDS/RV Datasheet PDF : 52 Pages
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WM8778
DEVICE DESCRIPTION
INTRODUCTION
WM8778 is a complete 2-channel DAC, 2-channel ADC audio CODEC, including digital interpolation
and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi-bit sigma delta
DACs with output smoothing filters. It is available in a single package and controlled by a 3 or 2-wire
serial interface or in a hardware mode.
An analogue bypass path option is available, to allow stereo analogue signals from the stereo inputs
to be sent to the stereo outputs. This allows a purely analogue input to analogue output high quality
signal path to be implemented if required.
The DAC and ADC have separate left/right clocks, bit clocks, master clocks and data I/Os. The
Audio Interface may be configured to operate in either master or slave mode. In Slave mode
ADCLRC, DACLRC, ADCBCLK and DACBCLK are all inputs. In Master mode ADCLRC, DACLRC,
ADCBCLK and DACBCLK are outputs.
The ADC has an analogue input PGA and a digital gain control, accessed by one register write. The
input PGA allows input signals to be gained up to +24dB and attenuated down to -21dB in 0.5dB
steps. The digital gain control allows attenuation from -21.5dB to -103dB in 0.5dB steps. This allows
the user maximum flexibility in the use of the ADC.
The DAC has its own digital volume control, which is adjustable between 0dB and -127.5dB in 0.5dB
steps. In addition a zero cross detect circuit is provided for digital volume controls. The digital
volume control detects a transition through the zero point before updating the volume. This
minimises audible clicks and ‘zipper’ noise as the gain values change.
The DAC output incorporates an input selector and mixer allowing a signal to be either switched into
the signal path in place of the DAC signal or mixed with the DAC signal before the analogue outputs.
Control of internal functionality of the device can be by 3-wire SPI compatible or 2-wire serial control
interface, or hardware mode, selected by the MODE pin. Both interfaces may be asynchronous to the
audio data interface as control data will be re-synchronised to the audio processing internally.
Operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided. In Slave
mode selection between clock rates is automatically controlled. In master mode the master clock to
sample rate ratio is set by control bits ADCRATE and DACRATE. ADC and DAC may run at different
rates. Master clock sample rates (fs) from less than 32kHz up to 192kHz are allowed, provided the
appropriate system clock is input.
The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP
serial port interface.
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The WM8778 uses separate master clocks for the ADC and DAC. The external master
system clocks can be applied directly through the ADCMCLK and DACMCLK input pins with no
software configuration necessary. In a system where there are a number of possible sources for the
reference clock it is recommended that the clock source with the lowest jitter be used to optimise the
performance of the ADC and DAC.
The master clock for WM8778 supports DAC audio sampling rates from 128fs to 768fs and ADC
sampling rates from 256fs to 512fs, where fs is the audio sampling frequency (DACLRC or ADCLRC)
typically 32kHz, 44.1kHz, 48kHz or 96kHz. The master clock is used to operate the digital filters and
the noise shaping circuits.
In Slave mode the WM8778 has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32 system
clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output
level at the last sample. The master clock must be synchronised with ADCLRC/DACLRC, although
the WM8778 is tolerant of phase variations or jitter on this clock. Table 6 shows the typical master
clock frequency inputs for the WM8778.
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PD, Rev 4.2, July 2008
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