WM8778SEDS/RV 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8778SEDS/RV Datasheet PDF : 52 Pages
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ZERO DETECT
WM8778
ADCBCLK and DACBCLK are also generated by the WM8778. The frequency of ADCBCLK and
DACBCLK depends on the mode of operation.
In 128/192fs modes (DACRATE=000 or 001) BCLK = MCLK/2. In 256/384/512fs modes
(ADCRATE/DACRATE=010 or 011 or 100) BCLK = MCLK/4. However if DSP mode is selected as
the audio interface mode then BCLK=MCLK. Note that DSP mode cannot be used in 128fs mode for
word lengths greater than 16 bits or in 192fs mode for word lengths greater than 24 bits.
The WM8778 has a zero detect circuit for each DAC channel, which detects when 1024 consecutive
zero samples have been input. The two zero flag outputs (ZFLAGL and ZFLAGR) may be
programmed to output the zero detect signals (see Table 9) that may then be used to control external
muting circuits. A ‘1’ on ZFLAGL or ZFLAGR indicates a zero detect. The zero detect may also be
used to automatically enable the mute by setting IZD. The zero flag output may be disabled by
setting DZFM to 00.
DZFM[1:0]
00
01
10
11
ZFLAGL
Zero flag disabled
Left channel zero
Both channel zero
Either channels zero
Table 9 Zero Flag Output Select
ZFLAGR
Zero flag disabled
Right channel zero
Both channel zero
Either channel zero
POWERDOWN MODES
The WM8778 has powerdown control bits allowing specific parts of the WM8778 to be powered off
when not being used. Control bit ADCPD powers off the ADC. The ADC input PGAs will be powered
down only if ADCPD and AINPD are set. When AINPD is set the bypass path is automatically
disabled. The stereo DAC has a separate powerdown control bit, DACPD allowing the DAC to be
powered off when not in use. This also switches the analogue outputs VOUTL/R to VMIDDAC to
maintain a dc level on the output. The output mixer will be disabled when PDWN is set.
Setting AINPD, ADCPD and DACPD will powerdown everything except the references VMIDADC,
ADCREF and VMIDDAC. ADCREF and VMIDDAC can be powered down by setting PDWN,
VMIDADC is always active. Setting PDWN will override all other powerdown control bits. It is
recommended that AINPD, ADCPD and DACPD are set before setting PDWN. The default is for all
blocks to be enabled.
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In
both Master and Slave modes DIN is always an input to the WM8778 and DOUT is always an output.
The default is Slave mode.
In Slave mode (MS=0) ADCLRC, DACLRC, ADCBCLK and DACBCLK are inputs to the WM8778
(Figure 11). DIN and DACLRC are sampled by the WM8778 on the rising edge of DACBCLK,
ADCLRC is sampled on the rising edge of ADCBCLK. ADC data is output on DOUT and changes on
the falling edge of ADCBCLK. By setting control bit BCLKINV the polarity of ADCBCLK and
DACBCLK may be reversed so that DIN and DACLRC are sampled on the falling edge of DACBCLK,
ADCLRC is sampled on the falling edge of ADCBCLK and DOUT changes on the rising edge of
ADCBCLK.
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PD, Rev 4.2, July 2008
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