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WM8778SEDS/RV 查看數據表(PDF) - Wolfson Microelectronics plc

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WM8778SEDS/RV
Wolfson
Wolfson Microelectronics plc Wolfson
WM8778SEDS/RV Datasheet PDF : 52 Pages
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Production Data
WM8778
In left justified, right justified and I2S modes; the minimum number of BCLKs per DACLRC/ADCLRC
period is 2 times the selected word length. ADCLRC/DACLRC must be high for a minimum of word
length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on
ADCLRC/DACLRC is acceptable provided the above requirements are met.
In DSP mode A or B, DACLRC is used as a frame sync signal to identify the MSB of the first word.
The minimum number of DACBCLKs per DACLRC period is 2 times the selected word length. Any
mark to space ratio is acceptable on DACLRC provided the rising edge is correctly positioned. The
ADC data may also be output in DSP mode A or B, with ADCLRC used as a frame sync to identify
the MSB of the first word. The minimum number of ADCBCLKs per ADCLRC period is 2 times the
selected word length.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN is sampled by the WM8778 on the first rising edge of
DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and
changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge
of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right
samples (Figure 13).
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
DIN/
DOUT
LEFT CHANNEL
123
MSB
n-2 n-1 n
LSB
1/fs
RIGHT CHANNEL
123
MSB
n-2 n-1 n
LSB
Figure 13 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN is sampled by the WM8778 on the rising edge of DACBCLK
preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the
falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of
ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples
(Figure 14).
1/fs
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
LEFT CHANNEL
DIN/
DOUT
123
MSB
n-2 n-1 n
LSB
Figure 14 Right Justified Mode Timing Diagram
RIGHT CHANNEL
123
MSB
n-2 n-1 n
LSB
w
PD, Rev 4.2, July 2008
19

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