WM8778SEDS/RV 查看數據表（PDF） - Wolfson Microelectronics plc

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WM8778SEDS/RV

24-bit, 192kHz Stereo CODEC

Wolfson Microelectronics plc 

WM8778

Production Data

I2S MODE

In I2S mode, the MSB of DIN is sampled by the WM8778 on the second rising edge of DACBCLK

following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the

first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising

edge of ADCBCLK. ADCLRC and DACLRC are low during the left samples and high during the right

samples.

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

LEFT CHANNEL

RIGHT CHANNEL

1 BCLK

123

MSB

n-2 n-1 n

LSB

1 BCLK

123

MSB

n-2 n-1 n

LSB

Figure 15 I2S Mode Timing Diagram

DSP MODES

In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A)

rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data

immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRC output will resemble the frame pulse shown in Figure 16 and Figure

17. In device slave mode, Figure 18 and Figure 19, it is possible to use any length of frame pulse

less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period

before the rising edge of the next frame pulse.

Figure 16 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)

w

PD, Rev 4.2, July 2008

20

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