CAT24C164
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. START/STOP Conditions
1 A2 A1 A0 a10 a9 a8 R/W CAT24C164
Figure 3. Slave Address Bits
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
1
8
BUS RELEASE DELAY (RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
ACK SETUP (≥ tSU:DAT)
SCL
tSU:STA
SDA IN
tF
tHIGH
tLOW
tLOW
tHD:STA
tHD:DAT
tR
tSU:DAT
SDA OUT
tAA
tDH
Figure 5. Bus Timing
tSU:STO
tBUF
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