25P10AV 查看數據表（PDF） - STMicroelectronics

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25P10AV

1 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface

STMicroelectronics 

Operating features

M25P10-A

4.5

Status Register

The Status Register contains a number of status and control bits, as shown in Table 6, that

can be read or set (as appropriate) by specific instructions. For a detailed description of the

Status Register bits, see Section 6.4: Read Status Register (RDSR).

4.6

Protection Modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can operate correctly in the presence of excessive noise. To help combat this, the

M25P10-A features the following data protection mechanisms:

● Power On Reset and an internal timer (tPUW) can provide protection against inadvertant

changes while the power supply is outside the operating specification.

● Program, Erase and Write Status Register instructions are checked that they consist of

a number of clock pulses that is a multiple of eight, before they are accepted for

execution.

● All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

– Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction completion

– Page Program (PP) instruction completion

– Sector Erase (SE) instruction completion

– Bulk Erase (BE) instruction completion

● The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-

only. This is the Software Protected Mode (SPM).

● The Write Protect (W) signal, in co-operation with the Status Register Write Disable

(SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable

(SRWD) bit to be write-protected. This is the Hardware Protected Mode (HPM).

● In addition to the low power consumption feature, the Deep Power-down mode offers

extra software protection, as all Write, Program and Erase instructions are ignored.

Table 2. Protected Area Sizes

Status Register

Content

Memory Content

BP1 Bit BP0 Bit

Protected Area

Unprotected Area

0

0 none

All sectors(1) (four sectors: 0, 1, 2 and 3)

0

1 Upper quarter (Sector 3)

Lower three-quarters (three sectors: 0

to 2)

1

0 Upper half (two sectors: 2 and 3)

Lower half (Sectors 0 and 1)

1

1 All sectors (four sectors: 0, 1, 2 and 3) none

1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) are 0.

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