25P10AV 查看數據表（PDF） - STMicroelectronics
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25P10AV Datasheet PDF : 50 Pages
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Instructions
M25P10-A
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
● by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
● or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
Figure 11. Write Status Register (WRSR) Instruction Sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
Status
Register In
D
76543210
High Impedance
MSB
Q
AI02282D
Table 7. Protection Modes
W SRWD
Signal Bit
Mode
Write Protection of the
Status Register
Memory Content
Protected Area(1)
Unprotected
Area(1)
1
0
Status Register is Writable (if
0
1
0
1
Software the WREN instruction has set
Protected the WEL bit)
(SPM) The values in the SRWD, BP1
and BP0 bits can be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program
and Sector Erase
instructions
Status Register is Hardware
0
1
Hardware write protected
Protected The values in the SRWD, BP1
(HPM) and BP0 bits cannot be
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program
and Sector Erase
instructions
changed
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
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