5. INTERFACE TIMING
(1)Timing Specifications
ITEM
SYMBOL MIN.
TYP.
MAX.
UNIT
Frequency
DCLK
*1) *4)
Period
Low Width
High Width
DATA *1) Set up time
(R,G,B,DENA,
HD, VD) Hold time
Horizontal Active Time
Horizontal Front Porch
DENA
*3)
Horizontal Back Porch
Vertical Active Time
Vertical Front Porch
Vertical Back Porch
HD
*2)*4)
Frequency
Period
Low Width
Frequency
VD *2) Period
[Note]
Low Width
fCLK
tCLK
tWCL
tWCH
tDS
tDH
tHA
tHFP
tHBP
tVA
tVFP
tVBP
fH
tH
tWHL
fV
tV
tWVL
30
25.0
8
8
2.3
7.3
512
0
6
768
0
4
--
16
1
55
13.3
1
32.5
30.8
--
--
--
--
512
12
148
768
3
35
48.4
20.7
68
60
16.7
6
40
33.3
--
--
--
--
512
--
--
768
--
--
62.5
--
--
75
18.2
--
MHz
ns
ns
ns
ns
ns
tCLK
tCLK
tCLK
tH
tH
tH
kHz
µs
tCLK
Hz
ms
tH
*1) DATA is latched at fall edge of DCLK in this specification.
*2) Polarities of HD and VD are negative in this specification.
*3) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
*4) DCLK should appear during all invalid period, and HD should appear during invalid period of
frame cycle.
T-51511D150-FW-A-AC (AC) No. 2002-0229
OPTREX CORPORATION
Page 7/33