CY2DP1510AXC 查看數據表（PDF） - Cypress Semiconductor

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CY2DP1510AXC

1:10 LVPECL Fanout Buffer with Selectable Clock Input

Cypress Semiconductor 

Pinouts

Figure 1. Pin Diagram – 32-Pin TQFP Package

VDD

Q2#

Q2

Q1#

Q1

Q0#

Q0

VDD

24 23 22 21 20 19 18 17

25

16

26

15

27

14

28

13

CY2DP1510

29

12

30

11

31

10

32

9

1234567 8

VDD

Q7

Q7#

Q8

Q8#

Q9

Q9#

VDD

CY2DP1510

Table 1. Pin Definitions

Pin No.

1, 9, 16, 25, 32

2

Pin Name

VDD

IN_SEL

Pin Type

Power

Input

3

IN0

4

IN0#

5

VBB

6

IN1

7

IN1#

8

VSS

10,12,14,17,19,21, Q(0:9)#

23,26,28,30

11,13,15,18,20,22, Q(0:9)

24,27,29,31

–

EPAD

Input

Input

Output

Input

Input

Power

Output

Output

–

Description

Power supply

Input clock select pin. Low-voltage complementary metal oxide

semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).

When IN_SEL = Low, the IN0/IN0# differential input pair is active

When IN_SEL = High, the IN1/IN1# differential input pair is active

LVPECL input clock. Active when IN_SEL = Low

LVPECL complementary input clock. Active when IN_SEL = Low

LVPECL reference voltage output

LVPECL input clock. Active when IN_SEL = High

LVPECL complementary input clock. Active when IN_SEL = High

Ground

LVPECL complementary output clocks

LVPECL output clocks

Exposed paddle. Connect to ground plane for package heat dissipation.

No electrical connection.

Document Number: 001-55566 Rev. *G

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