CY2DP1510AXC 查看數據表（PDF） - Cypress Semiconductor
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CY2DP1510AXC Datasheet PDF : 13 Pages
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CY2DP1510
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min
FIN
FOUT
VPP
tPD[7]
tODC[8]
tSK1[9]
tSK1
[9]
D
Input frequency
DC
Output frequency
FOUT = FIN
DC
LVPECL differential output voltage peak Fout = DC to 150 MHz
600
to peak, single ended. Terminated with
50 Ω to VDD – 2.0[6]
Fout = >150 MHz to 1.5 GHz
400
Propagation delay input pair to output Input rise/fall time < 1.5 ns
–
pair
(20% to 80%)
Output duty cycle
50% duty cycle at input
48
Frequency range up to 1 GHz
Output-to-output skew
Any output to any output, with
–
same load conditions at DUT
Device-to-device output skew
Any output to any output
–
between two or more devices.
Devices must have the same
input and have the same output
load.
PNADD
Additive RMS phase noise
Offset = 1 kHz
–
156.25-MHz input
Rise/fall time < 150 ps (20% to 80%)
Offset = 10 kHz
–
VID > 400 mV
Offset = 100 kHz
–
Offset = 1 MHz
–
Offset = 10 MHz
–
tJIT[10]
tR,tF[11]
Offset = 20 MHz
–
Additive RMS phase jitter (Random) 156.25 MHz, 12 kHz to 20 MHz –
offset; input rise/fall time <
150 ps (20% to 80%), VID >
400 mV
Output rise/fall time
50% duty cycle at input,
–
20% to 80% of full swing
(VOL to VOH)
Input rise/fall time < 1.5 ns
(20% to 80%)
Typ
Max Unit
–
1.5 GHz
–
1.5 GHz
–
–
mV
–
–
mV
–
600
ps
–
52
%
–
40
ps
–
150
ps
–
–120 dBc/Hz
–
–130 dBc/Hz
–
–140 dBc/Hz
–
–150 dBc/Hz
–
–154 dBc/Hz
–
–155 dBc/Hz
–
0.11
ps
–
300
ps
Notes
6. Refer to Figure 3 on page 7.
7. Refer to Figure 4 on page 7.
8. Refer to Figure 5 on page 7.
9. Refer to Figure 6 on page 8.
10. Refer to Figure 7 on page 8.
11. Refer to Figure 8 on page 8.
Document Number: 001-55566 Rev. *G
Page 6 of 13
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