CY2DP1510AXC 查看數據表（PDF） - Cypress Semiconductor

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CY2DP1510AXC

1:10 LVPECL Fanout Buffer with Selectable Clock Input

Cypress Semiconductor 

CY2DP1510

Figure 6. Output-to-Output and Device-to-Device Skew

QX

QX#

Device 1

QY

Device 2

QY#

QZ

QZ#

tSK1

tSK1 D

Figure 7. RMS Phase Jitter

Phase noise

Noise Power

Phase noise mark

Offset Frequency

f1

f2

RMS Jitter ∝ Area Under the Masked Phase Noise Plot

Figure 8. Output Rise/Fall Time

QX

80% 80%

VPP

20%

20%

QX#

tR

tF

Document Number: 001-55566 Rev. *G

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