MKL33Z128VLH4 查看數據表（PDF） - Freescale Semiconductor

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MKL33Z128VLH4

Kinetis KL33 With Up To 256 KB Flash 48 MHz Cortex-M0+ Based Microcontroller

Freescale Semiconductor 

General

Table 10. Low power mode peripheral adders — typical value (continued)

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85 105

ICMP

IUART

ITPM

nA

CMP peripheral adder measured by

22 22 22 22 22 22 µA

placing the device in VLLS1 mode with

CMP enabled using the 6-bit DAC and

a single external input for compare.

Includes 6-bit DAC power

consumption.

UART peripheral adder measured by

placing the device in STOP or VLPS

mode with selected clock source

waiting for RX data at 115200 baud

rate. Includes selected clock source

power consumption.

• IRC8M (8 MHz internal reference 114 114 114 114 114 114 µA

clock)

• IRC2M (2 MHz internal reference

34

34

34

34

34

34

clock)

TPM peripheral adder measured by

placing the device in STOP or VLPS

mode with selected clock source

configured for output compare

generating 100 Hz clock signal. No

load is placed on the I/O generating the

clock signal. Includes selected clock

source and I/O switching currents.

• IRC8M (8 MHz internal reference

µA

clock)

• IRC2M (2 MHz internal reference

clock)

147

147

147

147

147

147

42

42

42

42

42

42

IBG

Bandgap adder when BGEN bit is set 45 45 45 45 45 45 µA

and device is placed in VLPx or VLLSx

mode.

IADC

ADC peripheral adder combining the

330 330 330 330 330 330 µA

measured values at VDD and VDDA by

placing the device in STOP or VLPS

mode. ADC is configured for low power

mode using the internal clock and

continuous conversions.

ILCD

LCD peripheral adder measured by

4.5 4.5 4.5 4.5 4.5 4.5 µA

placing the device in VLLS1 mode with

external 32 kHz crystal enabled by

means of the OSC0_CR[EREFSTEN,

EREFSTEN] bits. VIREG disabled,

resistor bias network enabled, 1/8 duty

16

Freescale Semiconductor, Inc.

Kinetis KL33 With Up To 256 KB Flash, Rev3, 08/2014.

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