M1A3P250-FFGG144I 查看數據表（PDF） - Unspecified

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M1A3P250-FFGG144I

1 – ProASIC®3 Flash Family FPGAs with Optional Soft ARM Support

Unspecified 

ProASIC3 DC and Switching Characteristics

Power Consumption of Various Internal Resources

Table 2-11 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices

Device Specific Dynamic Power

(µW/MHz)

Parameter

Definition

PAC1

PAC2

PAC3

PAC4

Clock contribution of a Global Rib

14.50 12.80 12.80 11.00 11.00 9.30 9.30

Clock contribution of a Global Spine

2.48 1.85 1.35 1.58 0.81 0.81 0.41

Clock contribution of a VersaTile row

0.81

Clock contribution of a VersaTile used as a

0.12

sequential module

PAC5

First contribution of a VersaTile used as a

0.07

sequential module

PAC6

Second contribution of a VersaTile used as a

0.29

sequential module

PAC7

Contribution of a VersaTile used as a combinatorial

0.29

Module

PAC8

PAC9

Average contribution of a routing net

Contribution of an I/O input pin (standard-

dependent)

0.70

See Table 2-8 on page 2-7.

PAC10

Contribution of an I/O output pin (standard- See Table 2-8 on page 2-7 and Table 2-9 on

dependent)

page 2-7.

PAC11

Average contribution of a RAM block during a

read operation

25.00

PAC12

Average contribution of a RAM block during a

write operation

30.00

PAC13

Static PLL contribution

2.55 mW

PAC14

Dynamic contribution for PLL

2.60

* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Actel Libero® Integrated Design Environment (IDE).

v1.1

2-9

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