AD9633 查看數據表（PDF） - Analog Devices
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AD9633 Datasheet PDF : 42 Pages
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AD9633
VIN±x
CLK–
DDR
SDR
CLK+
DCO+
DCO–
DCO+
DCO–
FCO–
BITWISE
MODE
FCO+
D0–A
D0+A
D1–A
D1+A
FCO–
BYTEWISE
MODE
FCO+
D0–A
D0+A
D1–A
D1+A
VIN±x
CLK–
DDR
SDR
CLK+
DCO+
DCO–
DCO+
DCO–
FCO–
BITWISE
MODE
FCO+
D0–A
D0+A
D1–A
D1+A
FCO–
BYTEWISE
MODE
FCO+
D0–A
D0+A
D1–A
D1+A
N–1
tA
tEH
tCPD
N
tEL
Data Sheet
N+1
tFCO
tFRAME
tPD
tDATA
D08 D06 D04 D02 LSB D08 D06 D04 D02 LSB D08 D06 D04 D02
N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15
MSB
N – 17
D07
N – 17
D05
N – 17
D03
N – 17
D01
N – 17
MSB
N – 16
D07
N – 16
tLD
D05 D03
N – 16 N – 16
D01
N – 16
MSB
N – 15
D07
N – 15
D05
N – 15
D03
N – 15
D04 D03 D02 D01 LSB D04 D03 D02 D01 LSB D04 D03 D02 D01
N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15
MSB D08 D07 D06 D05 MSB D08 D07 D06 D05 MSB D08 D07 D06
N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15
Figure 3. 10-Bit DDR/SDR, Two-Lane, 1× Frame Mode
N–1
tA
N
N+1
tEH
tEL
tCPD
tFCO
tFRAME
tPD
tDATA
D10 D08 D06 D04 D02 LSB D10 D08 D06 D04 D02 LSB
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
MSB
N – 17
D09
N – 17
D07
N – 17
D05
N – 17
D03
N – 17
D01
N – 17
MSB
N – 16
D09
N – 16
tLD
D07 D05
N – 16 N – 16
D03
N – 16
D01
N – 16
D05 D04 D03 D02 D01 LSB D05 D04 D03 D02 D01 LSB
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
MSB D10 D09 D08 D07 D06 MSB D10 D09 D08 D07 D06
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
Figure 4. 12-Bit DDR/SDR, Two-Lane, 2× Frame Mode
Rev. B | Page 8 of 41
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