IS42S32200L-6TL 查看數據表（PDF） - Integrated Silicon Solution

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IS42S32200L-6TL

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Silicon Solution 

IS42S32200L, IS45S32200L

OPERATION

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued

to a bank within the SDRAM, a row in that bank must be

“opened.” This is accomplished via the ACTIVE command,

which selects both the bank and the row to be activated

(see Activating Specific Row Within Specific Bank).

After opening a row (issuing an ACTIVE command), a READ

or WRITE command may be issued to that row, subject to

the trcd specification. Minimum trcd should be divided by

the clock period and rounded up to the next whole number

to determine the earliest clock edge after the ACTIVE

command on which a READ or WRITE command can be

entered. For example, a trcd specification of 20ns with a

125 MHz clock (8ns period) results in 2.5 clocks, rounded

to 3. This is reflected in the following example, which cov-

ers any case where 2 < [trcd (MIN)/tck] ≤ 3. (The same

procedure is used to convert other specification limits from

time units to clock cycles).

A subsequent ACTIVE command to a different row in the

same bank can only be issued after the previous active

row has been “closed” (precharged). The minimum time

interval between successive ACTIVE commands to the

same bank is defined by trc.

A subsequent ACTIVE command to another bank can be

issued while the first bank is being accessed, which results

in a reduction of total row-access overhead. The minimum

time interval between successive ACTIVE commands to

different banks is defined by trrd.

Activating Specific Row Within Specific Bank

CLK

CKE HIGH

CS

RAS

CAS

WE

A0-A10

ROW ADDRESS

BA0, BA1

BANK ADDRESS

Example: Meeting trcd (MIN) when 2 < [trcd (min)/tck] ≤ 3

T0

T1

CLK

COMMAND ACTIVE

NOP

tRCD

T2

T3

T4

NOP

READ or

WRITE

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Integrated Silicon Solution, Inc. — www.issi.com

17

Rev.A

10/17/2012

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