74LVC109D,118 查看數據表（PDF） - NXP Semiconductors.

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74LVC109D,118

Dual JK flip-flop with set and reset; positive-edge trigger

NXP Semiconductors. 

Philips Semiconductors

Dual JK flip-flop with set and reset;

positive-edge trigger

AC WAVEFORMS

Product specification

74LVC109

handbook, full pagewidth

VI

nJ, nK input

GND

VI

nCP input

GND

VOH

nQ output

VOL

VOH

nQ output

VOL

VM

th

t su

th

t su

1/fmax

VM

tW

t PHL

VM

t PLH

VM

t PLH

t PHL

MNA860

VM = 1.5 V at VCC ≥ 2.7 V.

VM = 0.5VCC at VCC < 2.7 V.

VOL and VOH are typical output voltage drop that occur with the output load.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig.6 Clock input (nCP) to output (nQ and nQ) propagation delays, the clock pulse width, the nJ and nK to nCP

set-up, the nCP to nJ and nK hold times and the maximum clock pulse frequency.

2004 Mar 18

11

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