EN80C186EA13 查看數據表（PDF） - Intel

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EN80C186EA13

16-Bit High-Integration Embedded Processors

Intel 

Intel® 80C186XL and Intel® 80C186EA Differences

Table 5.

Pin Descriptions (Sheet 1 of 3)

Pin Name

VCC

VSS

CLKIN

OSCOUT

CLKOUT

RESIN

RESOUT

PDTMR

NMI

TEST/BUSY

(TEST)

AD15:0

(AD7:0)

A18:16

A19/S6–A16

(A19–A8)

Pin

Type

P

G

I

O

O

I

O

I/O

I

I

I/O

O

Input

Type

A(E)

A(L)

A(L)

A(E)

A(E)

S(L)

Output

States

Description

H(Q)

R(Q)

P(Q)

H(Q)

R(Q)

P(Q)

H(0)

R(I)

P(O)

H(WH)

R(Z)

P(1)

H(Z)

R(Z)

P(X)

H(Z)

R(Z)

P(X)

POWER connections consist of six pins which must be shorted

externally to a VCC board plane.

GROUND connections consist of five pins which must be shorted

externally to a VSS board plane.

CLocK INput is an input for an external clock. An external oscillator

operating at two times the required processor operating frequency can

be connected to CLKIN. For crystal operation, CLKIN (along with

OSCOUT) are the crystal connections to an internal Pierce oscillator.

OSCillator OUTput is only used when using a crystal to generate the

external clock. OSCOUT (along with CLKIN) are the crystal R(Q)

connections to an internal Pierce oscillator. This pin is not to be P(Q)

used as 2X clock output for non-crystal applications (i.e., this pin is N.C.

for non-crystal applications). OSCOUT does not float in ONCE mode.

CLocK OUTput provides a timing reference for inputs and outputs of the

processor, and is one-half the input clock (CLKIN) frequency. CLKOUT

has a 50% duty cycle and transitions every falling edge of CLKIN.

RESet IN causes the processor to immediately terminate any bus cycle

in progress and assume an initialized state. All pins will be driven to a

known state, and RESOUT will also be driven active. The rising edge

(low-to-high) transition synchronizes CLKOUT with CLKIN before the

processor begins fetching opcodes at memory location 0FFFF0H.

RESet OUTput that indicates the processor is currently in the reset

state. RESOUT will remain active as long as RESIN remains active.

When tied to the TEST/BUSY pin, RESOUT forces the 80C186EA into

Numerics Mode.

Power-Down TiMeR pin (normally connected to an external capacitor)

that determines the amount of time the processor waits after an exit from

power down before resuming normal operation. P(1) The duration of time

required will depend on the startup characteristics of the crystal

oscillator.

Non-Maskable Interrupt input causes a Type 2 interrupt to be serviced

by the CPU. NMI is latched internally.

TEST/BUSY is sampled upon reset to determine whether the 80C186EA

is to enter Numerics Mode. In regular operation, the pin is TEST. TEST is

used during the execution of the WAIT instruction to suspend CPU

operation until the pin is sampled active (low). In Numerics Mode, the pin

is BUSY. BUSY notifies the 80C186EA of 80C187 Numerics

Coprocessor activity.

These pins provide a multiplexed Address and Data bus. During the

address phase of the bus cycle, address bits 0 through 15 (0 through 7

on the 8-bit bus versions) are presented on the bus and can be latched

using ALE. 8- or 16-bit data information is transferred during the data

phase of the bus cycle.

These pins provide multiplexed Address during the address phase of

the bus cycle. Address bits 16 through 19 are presented on these pins

and can be latched using ALE. A18:16 are driven to a logic 0 during the

data phase of the bus cycle. On the 8-bit bus versions, A15–A8 provide

valid address information for the entire bus cycle. Also during the data

phase, S6 is driven to a logic 0 to indicate a CPU-initiated bus cycle or

logic 1 to indicate a DMA-initiated bus cycle or a refresh cycle.

Product Name Datasheet

19

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