EN80C186EA25 查看數據表（PDF） - Intel

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EN80C186EA25

16-Bit High-Integration Embedded Processors

Intel 

Intel® 80C186XL and Intel® 80C186EA Differences

Table 5.

Pin Descriptions (Sheet 3 of 3)

Pin Name

Pin Input Output

Type Type States

Description

HOLD

I

A(L)

HOLD request input to signal that an external bus master wishes to gain

control of the local bus. The processor will relinquish control of the local

bus between instruction boundaries not conditioned by a LOCK prefix.

HLDA

O

H(1) HoLD Acknowledge output to indicate that the processor has

R(0) relinquished control of the local bus. When HLDA is asserted, the

P(0) processor will (or has) floated its data bus and control signals allowing

another bus master to drive the signals directly.

UCS

O

H(1) Upper Chip Select will go active whenever the address of a memory or

R(1) I/O bus cycle is within the address limitations programmed by the user.

P(1) After reset, UCS is configured to be active for memory accesses

between 0FFC00H and 0FFFFFH. During a processor reset, UCS and

LCS are used to enable ONCE Mode.

LCS

O

H(1) Lower Chip Select will go active whenever the address of a memory

R(1) bus cycle is within the address limitations programmed by the user. R(1)

P(1) LCS is inactive after a reset. During a processor reset, UCS and LCS are

used to enable ONCE Mode.

MCS0/PEREQ

MCS1/ERROR

MCS2

MCS3/NCS

I/O A(L) H(1) These pins provide a multiplexed function. If enabled, these pins

R(1) normally comprise a block of Mid-Range Chip Select outputs which will

P(1) go active whenever the address of a memory bus cycle is within the

address limitations programmed by the user. In Numerics Mode

(80C186EA only), three of the pins become handshaking pins for the

80C187. The CoProcessor REQuest input signals that a data transfer is

pending. ERROR is an input which indicates that the previous numerics

coprocessor operation resulted in an exception condition. An interrupt

Type 16 is generated when ERROR is sampled active at the beginning of

a numerics operation. Numerics Coprocessor Select is an output

signal generated when the processor accesses the 80C187.

PCS4:0

O

H(1)

R(1)

P(1)

Peripheral Chip Selects go active whenever the address of a memory

or I/O bus cycle is within the address limitations programmed by the

user.

PCS5/A1

O

PCS6/A2

H(1)/

H(X)

R(1)

P(1)

These pins provide a multiplexed function. As additional Peripheral

Chip Selects, they go active whenever the address of a memory or

I/O bus cycle is within the address limitations by the user. They may also

be programmed to provide latched Address A2:1 signals.

T0OUT

O

T1OUT

H(Q)

R(1)

P(Q)

Timer OUTput pins can be programmed to provide a single clock or

continuous waveform generation, depending on the timer mode

selected.

T0IN

I

A(L) Timer INput is used either as clock or control signals, depending on the

A(E) timer mode selected. T1IN A(E)

DRQ0

DRQ1

I

A(L)

DMA ReQuest is asserted by an external request when it is prepared for

a DMA transfer.

INT0

INT1/SELECT

I A(E,L)

Maskable INTerrupt input will cause a vector to a specific Type interrupt

routine. To allow interrupt expansion, INT0 and/or INT1 can be used with

INTA0 and INTA1 to interface with an external slave controller. INT1

becomes SELECT when the ICU is configured for Slave Mode.

INT2/INTA0

INT3/INTA1/IRQ

I/O A(E,L) H(1) These pins provide multiplexed functions. As inputs, they provide a

R(Z) maskable INTerrupt that will cause the CPU to vector to a specific Type

P(1) interrupt routine. As outputs, each is programmatically controlled to

provide an INTerrupt Acknowledge handshake signal to allow interrupt

expansion. INT3/INTA1 becomes IRQ when the ICU is configured for

Slave Mode.

N.C.

No Connect. For compatibility with future products, do not connect to

these pins.

NOTE: Pin names in parentheses apply to the 80C188EA and 80L188EA.

Product Name Datasheet

21

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