LPC1817JBD144 查看數據表（PDF） - NXP Semiconductors.

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LPC1817JBD144

32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC

NXP Semiconductors. 

NXP Semiconductors

5. Block diagram

LPC185x/3x/2x/1x

32-bit ARM Cortex-M3 microcontroller

SWD/TRACE PORT/JTAG

LPC185x/3x/2x/1x

HIGH-SPEED PHY

TEST/DEBUG

ETM INTERFACE

ARM

CORTEX-M3

DMA

ETHERNET(1)

10/100

MAC

IEEE 1588

HIGH-

SPEED

USB0(1)

HOST/

DEVICE/

OTG

USB1(1)

HOST/

DEVICE

LCD(1)

SD/

MMC

masters

AHB MULTILAYER MATRIX

64 kB ROM

32 kB LOCAL SRAM

40 kB LOCAL SRAM

32 kB AHB SRAM

16 kB +

16 kB AHB SRAM

16 kB EEPROM

512/256 kB FLASH A

512/256 kB FLASH B

slaves

BRIDGE 0

BRIDGE 1

BRIDGE 2

BRIDGE 3

BRIDGE

slaves

BRIDGE

WWDT

USART0

UART1

SSP0

TIMER0

TIMER1

MOTOR

CONTROL

PWM(1)

I2C0

I2S0

I2S1

C_CAN1

SCU

GPIO PIN

INTERRUPTS

GPIO GROUP0

INTERRUPT

GPIO GROUP1

INTERRUPT

RI TIMER

USART2

USART3

TIMER2

TIMER3

SSP1

QEI(1)

GIMA

I2C1

10-bit DAC

C_CAN0

10-bit ADC0

10-bit ADC1

CGU

CCU1

CCU2

RGU

ALARM TIMER

BACKUP REGISTERS

POWER MODE CONTROL

CONFIGURATION

REGISTERS

EVENT ROUTER

OTP MEMORY

RTC

RTC OSC

12 MHz IRC

EVENT MONITOR

RTC POWER DOMAIN

SPIFI

EMC

HS GPIO

SCT

= connected to DMA

(1) Not available on all parts. See Table 2.

Fig 1. LPC185x/3x/2x/1x block diagram

002aah225

LPC185X_3X_2X_1X

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5.2 — 8 March 2016

© NXP B.V. 2016. All rights reserved.

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