AD7249(2000) 查看數據表（PDF） - Analog Devices

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AD7249
(Rev.:2000)

LC2MOS Dual 12-Bit Serial DACPORT

Analog Devices 

AD7249

DIGITAL INTERFACE

The AD7249 contains an input serial to parallel shift register

and a DAC latch for both DAC A and DAC B. A simplified

diagram of the input loading circuitry is shown in Figure 7.

Serial data on the SDIN input is loaded to the input register

under control of SYNC and SCLK. The SYNC input provides

the frame synchronization signal which tells the AD7249 that

valid serial data on the SDIN input will be available for the next

16 falling edges of SCLK. An internal counter/decoder circuit

provides a low gating signal so that only 16 data bits are clocked

into the input shift register. After 16 SCLK pulses the internal

gating signal goes inactive (high) thus locking out any further

clock pulses. Therefore either a continuous clock or a burst

clock source may be used to clock in the data. The SYNC input

is taken high after the complete 16-bit word is loaded in.

DAC selection is accomplished using the thirteenth bit (DB12)

of the serial data input stream. A zero in DB12 will select DAC

A while a one in this position selects DAC B. Although 16 bits

of data are clocked into the input register, only 12 bits get trans-

ferred into the DAC latch. The relevant DAC latch is deter-

mined by the value of the thirteenth bit and the first three bits

in the 16-bit stream are don’t cares. Therefore, the data format

is three don’t cares followed by the DAC selection bit and the

12-bit data word with the LSB as the last bit in the serial

stream.

There are two ways in which a DAC latches and hence the

analog outputs may be updated. The status of the LDAC input

is examined after SYNC is taken low. Depending on its status,

one of two update modes are selected.

If LDAC = 0, then the automatic update mode is selected. In

this mode the DAC latch and analog output are updated auto-

matically when the last bit in the serial data stream is clocked in.

The update thus takes place on the sixteenth falling SCLK edge.

If LDAC = 1, then the automatic update is disabled and both

DAC latches are updated by taking LDAC low any time after

the 16-bit data transfer is complete. The update now occurs on

the falling edge of LDAC. Note that the LDAC input must be

taken back high again before the next data transfer is initiated.

When a complete word is held in the shift register it may then

be loaded into the DAC latch under control of LDAC.

Clear Function (CLR)

The clear function clears the contents of the input shift register

and loads both DAC latches with all 0s. It is activated by taking

CLR low. In all ranges except the Offset Binary bipolar range

(–5 V to +5 V) the output voltage is reset to 0 V. In the offset

binary bipolar range the output is set to –REFIN. The clear

function is especially useful at power-up as it enables the output

to be reset to a known state.

SYNC

SCLK

SDIN

LDAC

CLR

RESET

/16

COUNTER/

DECOUNTER

GATING

SIGNAL

CLK A

DECODER

SDATA

CLK B

AUTO-UPDATE

CIRCUITRY

DAC LATCH A (12-BITS)

SHIFT REGISTER A

SHIFT REGISTER B

DAC LATCH B (12-BITS)

Figure 7. Simplified Loading Structure

REV. C

–7–

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