ISPXPLD5512MX 查看數據表（PDF） - Lattice Semiconductor

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ISPXPLD5512MX

3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor 

Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

Figure 17. I/O Cell

Shared PTOE 0

Shared PTOE 1

Shared PTOE 2

Shared PTOE 3

PTOE

GOE0

GOE1

TOE

Data Output from

Primary Macrocell

Data Output from

Alternate Macrocells

Output Sharing

Array (OSA)

To Adjacent I/O Pad

Data Input to Routing

To Primary

Macrocell

Delay Element

To Alternate

Macrocell

Output Buffer

(VCCO Independent

for Open Drain

Outputs)

VCCO for

this Bank

VCCO to All

Other I/Os

in Bank

Differential

GND

Output Buffer

I/O

CMOS/TTL

Pad

Input Buffer

(VREF Independent)

+

–

VREF Dependent

Input Buffer

VREF to All

other I/Os in Bank

+

–

Differential

I/O Buffer

To Adjacent

I/O Pad

Table 10. Shared PTOE Segments

Device

ispXPLD 5256MX

ispXPLD 5512MX

ispXPLD 5768MX

ispXPLD 51024MX

MFBs Associated With Segments

(A, B, C, D) (E, F, G, H)

(A, B, C, D) (E, F, G, H)

(I, J, K, L) (M, N, O, P)

(A, B, C, D) (E, F, G, H)

(I, J, K, L) (M, N, O, P)

(Q, R, S, T) (U, V, W, Z)

(A, B, C, D) (E, F, G, H)

(I, J, K, L) (M, N, O, P)

(Q, R, S, T) (U, V, W, Z)

(Y, Z, AA, AB) (AC, AD, AE, AF)

sysIO Standards

Each I/O within a bank is individually configurable based on the VCCO and VREF settings. Some standards also

require the use of an external termination voltage. Table 12 lists the sysIO standards with the typical values for

VCCO, VREF and VTT. For more information on the sysIO capability, please refer to Lattice technical note number

TN1000, sysIO Usage Guidelines for Lattice Devices, available at www.latticesemi.com.

Table 11. Number of I/Os per Bank

Device

ispXPLD 5256MX

ispXPLD 5512MX

ispXPLD 5768MX

ispXPLD 51024MX

Maximum Number of I/Os per Bank (n)

36

68

96

96

18

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