CY8C5488LTI-LP093 查看數據表（PDF） - Cypress Semiconductor

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CY8C5488LTI-LP093

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PSoC® 5LP: CY8C54LP Family

Datasheet

1. Architectural Overview

Introducing the CY8C54LP family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit

PSoC 3 and 32-bit PSoC 5LP platform. The CY8C54LP family provides configurable blocks of analog, digital, and interconnect circuitry

around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables

a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure 1-1. Simplified Block Diagram

4- 25 MHz

( Optional)

32.768 kHz

( Optional)

System Wide

Resources

Xtal

Osc

IMO

RTC

Timer

WDT

and

Wake

ILO

Clocking System

Power Management

System

POR and

LVD

Sleep

Power

1.8V LDO

SMP

Digital Interconnect

Analog Interconnect

Digital System

Universal Digital Block Array (24 x UDB)

8- Bit

Timer

Quadrature Decoder

UDB

UDB

16 -Bit

PWM

UDB

16 -Bit PRS

UDB

UDB

UDB

UDB

I 2C Slave

UDB

UDB

8- Bit SPI

UDB

UDB

UART

UDB

UDB

12- Bit SPI

UDB

UDB

8- Bit

Timer Logic

UDB

Logic

UDB

12- Bit PWM

UDB

UDB

UDB

UDB

UDB

UDB

UDB

I2C

Master /

Slave

4x

Timer

Counter

PWM

FS USB

2.0

System Bus

Memory System

EEPROM

SRAM

CPU System

Cortex M 3 CPU

Interrupt

Controller

EMIF

Flash

Cache

Controller

PHUB

DMA

Program &

Debug

Program

Debug &

Trace

Boundary

Scan

USB

PHY

22 Ω

LCD Direct

Drive

2 x SC/CT Blocks

(TIA, PGA, Mixer etc)

Temperature

Sensor

CapSense

2 x DAC

Analog System

ADC

SAR

ADC

+

2x

Opamp

-

+

4x

CMP

-

3 per

Opamp

0. 5 to5.5V

( Optiona)l

Document Number: 001-84934 Rev. *E

Page 4 of 120

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