CY8C5488LTI-LP093 查看數據表（PDF） - Cypress Semiconductor
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CY8C5488LTI-LP093 Datasheet PDF : 120 Pages
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PSoC® 5LP: CY8C54LP Family
Datasheet
Figure 2-5 and Figure 2-6 show an example schematic and an
example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a 2-layer board.
The two pins labeled VDDD must be connected together.
The two pins labeled VCCD must be connected together, with
capacitance added, as shown in Figure 2-5 and Power System
on page 26. The trace between the two VCCD pins should be
as short as possible.
The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals,
refer to the application note AN57821 - Mixed Signal Circuit
Board Layout Considerations for PSoC® 3 and PSoC 5.
Figure 2-5. Example Schematic for 100-Pin TQFP Part with Power Connections
VDDD
VDDD
VDDD
C6
0.1 UF
VSSD
C1
1 UF
VSSD
C2
0.1 UF
VCCD
VSSD
VSSD
1
2
3
4
5
6
7
8
9
10
11
12
13
VSSD 14
15
16
17
18
19
20
21
22
23
24
25
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWDIO, TMS
P1[1], SWDCK, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], NTRST
VDDIO0
OA0-, REF0, P0[3]
OA0+, SAR1REF, P0[2]
OA0OUT, P0[1]
OA2OUT, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
KHZXIN, P15[3]
KHZXOUT, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3OUT, P3[7]
OA1OUT, P3[6]
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDD
VDDA
C8
0.1 UF
C17
1 UF
VSSD
VSSD
VDDA
VSSA
VCCA
VSSA
VSSD
VDDA
C9
1 UF
C10
0.1 UF
VSSA
VDDD
C12
0.1 UF
VSSD
C16
0.1 UF
C15
1 UF
VDDD
C11
0.1 UF
VSSD
VSSD
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-6.
Document Number: 001-84934 Rev. *E
Page 9 of 120
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