7005S17GGB8 查看數據表（PDF） - Integrated Device Technology
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7005S17GGB8 Datasheet PDF : 21 Pages
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IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7005X15
Com'l Only
7005X17
Com'l Only
Symbol
Parameter
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
tBDA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable Low
tBDC
BUSY Access Time from Chip Enable High
tAPS
Arbitration Priority Set-up Time(2)
tBDD
BUSY Disable to Valid Data(3)
tWH
Write Hold After BUSY(5)
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
Min. Max. Min. Max.
____
15
____
17
____
15
____
17
____
15
____
17
____
15
____
17
5
____
5
____
____
18
____
18
12
____
13
____
0
____
12
____
0
____
13
____
____
30
____
30
____
25
____
25
7005X20
Com'l, Ind
& Military
Min. Max.
____
20
____
20
____
20
____
17
5
____
____
30
15
____
0
____
15
____
____
45
____
35
7005X25
Com'l &
Military
Min. Max. Unit
____
20
ns
____
20
ns
____
20
ns
____
17
ns
5
____
ns
____
30
ns
17
____
ns
0
____
ns
17
____
ns
____
50
ns
____
35
ns
2738 tbl 15a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind &
Military
7005X70
Military
Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
20
____
45
____
45
ns
tBDA
BUSY Disable Time from Address Not Matched
____
20
____
40
____
40
ns
tBAC
BUSY Acce ss Time from Chip Enable Low
____
20
____
40
____
40
ns
tBDC
BUSY Acce ss Time from Chip Enable High
____
20
____
35
____
35
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Date(3)
____
35
____
40
____
45
ns
tWH
Write Hold After BUSY(5)
25
____
25
____
25
____
ns
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write(4)
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
25
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
60
____
80
____
95
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
45
____
65
____
80
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (S or L).
2738 tbl 15b
61.422
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