7005S17JGI 查看數據表（PDF） - Integrated Device Technology
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7005S17JGI Datasheet PDF : 21 Pages
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IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Waveform of Interrupt Timing(1)
tWC
Military, Industrial and Commercial Temperature Ranges
ADDR"A"
CE"A"
tAS(3)
INTERRUPT SET ADDRESS(2)
tWR(4)
R/W"A"
INT"B"
ADDR"B"
CE"B"
tINS(3)
tAS(3)
tRC
INTERRUPT CLEAR ADDRESS(2)
2738 drw 17
OE"B"
INT"B"
tINR(3)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
2738 drw 18
Truth Table III — Interrupt Flag(1,4)
Left Port
R/WL
CEL
OEL
A12L-A0L
INTL
R/WR
CER
L
L
X
1FFF
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L(3)
L
L
X
L
L
1FFE
H(2)
X
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
Right Port
OER
A12R-A0R
X
X
L
1FFF
X
1FFE
X
X
INTR
Function
L(2) Set Right INTR Flag
H(3) Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
2738 tbl 17
61.452
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