EELXT905PC.C2 查看數據表（PDF） - Intel

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EELXT905PC.C2

Universal 10BASE-T Transceiver with 3.3V Support

Intel 

LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

2.4

Jabber Control Function

Figure 4 is a state diagram of the LXT905 jabber control function. The LXT905 on-chip Watch-

Dog Timer (WDT) prevents the DTE from locking into a continuous transmit mode. When a

transmission exceeds the time limit, the WDT disables the transmit and loopback functions and

activates the COL pin. Once the LXT905 is in the jabber state, the TXD circuit must remain idle

for a period of 0.25 to 0.75 seconds before it exits the jabber state.

Figure 4. Jabber Control Function

Power On

No Output

DO=Active

Nonjabber Output

Start_XMIT_MAX_Timer

DO=Idle

DO=Active ∗

XMIT_Max_Timer_Done

Jab

XMIT=Disable

LPBK=Disable

CI=SQE

DO=Idle

Unjab Wait

Start_Unjab_Timer

XMIT=Disable

LPBK=Disable

CI=SQE

Unjab_ Timer_Done DO=Active ∗

Unjab_Timer_Not_Done

12

Datasheet

Document #: 249271

Revision #: 002

Rev. Date: June 19, 2001

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