HEF4046B 查看數據表（PDF） - NXP Semiconductors.

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HEF4046B

Phase-locked loop

NXP Semiconductors. 

NXP Semiconductors

HEF4046B

Phase-locked loop

102

R2

R1

10

1

10−1

(1) (2)

001aae634

105

P

(μW)

104

103

102

001aae635

(1)

(2)

(3)

(4)

(5)

(6)

10−2

1

10

102

103

fmax/fmax

10

1

10

102

103

R1 (kΩ)

Line (1): VDD = 5 V;

Line (2): VDD = 10 V, 15 V.

Fig 9. Typical ratio of R2/R1 as a function of the ratio

fmax/fmin

R2 = ; VCO_IN at 0.5VDD; CL = 50 pF.

Lines (1) and (2): VDD = 15 V;

Lines (3) and (4): VDD = 10 V;

Lines (5) and (6): VDD = 5 V;

Lines (1), (3), and (5): C1 = 50 pF;

Lines (2), (4), and (6): C1 = 1 F.

Fig 10. Power dissipation as a function of R1

106

P

(μW)

105

001aae636

104

103

102

1

(1)

(2)

(3)

(4)

(5)

(6)

10

102

103

R2 (kΩ)

R1 = ; VCO_IN at VSS (0 V); CL = 50 pF.

Lines (1) and (2): VDD = 15 V;

Lines (3) and (4): VDD = 10 V;

Lines (5) and (6): VDD = 5 V;

Lines (1), (3), and (5): C1 = 50 pF;

Lines (2), (4), and (6): C1 = 1 F.

Fig 11. Power dissipation as a function of R2

104

P

(μW)

103

102

10

001aae637

(1)

(2)

(3)

1

1

10

102

103

RSF (kΩ)

VCO_IN at 0.5VDD; R1 = ; R2 = .

Line (1): VDD = 15 V;

Line (2): VDD = 10 V;

Line (3): VDD = 5 V.

Fig 12. Power dissipation of source follower as a

function of RL

HEF4046B

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 18 November 2011

© NXP B.V. 2011. All rights reserved.

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