H5TQ2G43CFR-XXC 查看數據表（PDF） - Hynix Semiconductor

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H5TQ2G43CFR-XXC

2Gb DDR3 SDRAM

Hynix Semiconductor 

Symbol

Precharge Standby Current

Description

IDD2N

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;

Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable

at 0; Pattern Details: see Table 5.

Precharge Standby ODT Current

IDD2NT

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0;

Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: tog-

gling according to Table 6; Pattern Details: see Table 6.

Precharge Power-Down Current Slow Exit

IDD2P0

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down

Mode: Slow Exitc)

Precharge Power-Down Current Fast Exit

IDD2P1

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down

Mode: Fast Exitc)

Precharge Quiet Standby Current

IDD2Q

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0

Active Standby Current

IDD3N

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;

Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable

at 0; Pattern Details: see Table 5.

Rev. 1.0 / Apr. 2013

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