H5TQ2G43CFR-XXC 查看數據表（PDF） - Hynix Semiconductor

零件编号

产品描述 (功能)

生产厂家

H5TQ2G43CFR-XXC

2Gb DDR3 SDRAM

Hynix Semiconductor 

Speed Bin Table Notes

Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-

ing a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as require-

ments from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-

nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should

use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat-

ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =

3.0 ns should only be used for CL = 5 calculation.

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)

down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is

tCK(AVG).MAX corresponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-

datory feature. Refer to Hynix DIMM data sheet and/or the DIMM SPD information if and how this set-

ting is supported.

6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the

table which are not subject to Production Tests but verified by Design/Characterization.

7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the

table which are not subject to Production Tests but verified by Design/Characterization.

8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the

table which are not subject to Production Tests but verified by Design/Characterization.

9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the

table which are not subject to Production Tests but verified by Design/Characterization.

10. Any DDR3-2133 speed bin also supports functional operation at lower frequencies as shown in the

table which are not subject to Production Tests but verified by Design/Characterization

11. Hynix DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP

must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H

devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin

(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to

DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin

(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)

also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125

ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.

12. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.

13. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not manda-

tory in SPD coding.

14. Hynix DDR3 SDRAM devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/

tRPmin must be 13.125ns. SPD setting must be programed to match. For example, DDR3-1866

devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in

SPD bytes for tAAmin(byte 16), tRCDmin(byte 18) and tRPmin(byte 20) is programmed to 13.125ns,

tRCmin(byte 21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRP-

min = 34ns + 13.125ns)

Rev. 1.0 / Apr. 2013

32

Share Link: